1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to a semiconductor device having a structure suitable for imparting high reliability to semiconductors with a multi-layer wiring structure.
2. Description of the Background Art
With recent increase in integration and functions of semiconductor devices, wirings have become increasingly finer, the number of wiring layers has increased, and the multi-layer wiring technique has become essential. FIG. 1 shows a cross-sectional view of a semiconductor device of a two-layer wiring structure formed using a conventional multi-layer wiring technique.
In FIG. 1, a first interlayer insulating film 12 is formed on a silicon substrate 10. On the first interlayer insulating film 12 is provided a lower layer metal wiring 14 made of aluminum or the like. The lower layer metal wiring 14 is covered with a fluorine-containing silicon oxide film 16. On the fluorine-containing silicon oxide film 16 is formed a TEOS-based silicon oxide film 18 (hereafter referred to as xe2x80x9cTEOS film 18xe2x80x9d).
In semiconductor devices of the generation in which sub-quarter-micron wirings are used, especially in the ones for which high-speed operation is required, the capacitance of the interlayer insulating film must be sufficiently small. Since the fluorine-containing silicon oxide film 16 is more suitable for decrease in capacitance than a silicon oxide film that does not contain fluorine, the fluorine-containing silicon oxide film has been used as a part of the interlayer insulating film in such a semiconductor device.
On the TEOS film 18 is formed a metal wiring 20 made of aluminum or the like. The metal wiring 20 is covered with a silicon nitride film 22 that acts as a passivation film.
The method for manufacturing a conventional semiconductor device shown in FIG. 1 will be described below referring to FIGS. 2 to 4.
As shown in FIG. 2, a first interlayer insulating film 12, and a lower layer metal wiring 14 are first formed on a silicon substrate 10 using the combination of the CVD method, the etch-back method, the CMP method or the like.
A fluorine-containing silicon oxide layer 16 is deposited on the entire surface of the semiconductor wafer so as to cover the first interlayer insulating film 12 and the lower layer metal wiring 14. The fluorine-containing silicon oxide layer 16 is formed using the high-density plasma CVD method that uses SiH4 gas, O2 gas, and C2F6 gas as the reaction gases, that is, the CVD method to generate high-density plasma by impressing a bias voltage to the above-mentioned reaction gases. In such high-density plasma CVD method, deposition and sputter etching proceed simultaneously. Therefore, the portion having a step beneath it, that is, the portion above the lower layer metal wiring 14 has its corners etched off to have a triangular shape. The fluorine-containing silicon oxide layer 16 is deposited until the thickness thereof becomes substantially the same as that of the lower layer metal wiring 14.
As shown in FIG. 3, a TEOS film 18 is deposited on the fluorine-containing silicon oxide layer 16. The TEOS film 18 is formed by, for example, the plasma CVD method that uses TEOS and O2 gas as reaction gases. The underlying shapes are exactly reflected to the surface of a silicon oxide film formed by such CVD method. Therefore, the portion of the TEOS film 18 above the lower layer metal wiring 14 has a triangular shape.
As shown in FIG. 4, the TEOS film 18 is planarized by the CMP method. This CMP method is performed so that the TEOS film 18 is left above the lower layer metal wiring 14, that is, so that the fluorine-containing silicon oxide layer 16 is not exposed on the surface of the TEOS film 18. Via holes (not shown) to the lower layer metal wiring 14 are formed in the fluorine-containing silicon oxide layer 16 and the TEOS film 18. In the via holes are formed tungsten plugs (not shown). The via holes and the tungsten plugs are formed using the combination of photoengraving, dry etching, sputtering, the CVD method, or the etch-back method.
Thereafter, a metal wiring 20 (see FIG. 1) is patterned on the TEOS film 18 so as to conduct to the above-described tungsten plugs, and a silicon nitride film 22 that acts as a passivation film is formed on the upper layer by the plasma CVD method. After a bonding pad section (not shown) is opened in the silicon nitride film 22, the semiconductor device having the multiple wiring structure shown in FIG. 1 is completed.
After the fluorine-containing silicon oxide layer 16 and the TEOS film 18 have been formed in the above-described conventional manufacturing method, the step of forming a tungsten film by the CVD method, the step of forming an aluminum film by sputtering, or the step of forming a silicon nitride film 22 by the plasma CVD method are performed. These steps are performed in high temperature atmospheres at about 400xc2x0 C. Also in processes for manufacturing semiconductor devices, after the fluorine-containing silicon oxide layer 16 and the TEOS film 18 have been formed, heat treatment at a temperature of about 400xc2x0 C. may be performed for stabilizing device characteristics.
Fluorine contained in the fluorine-containing silicon oxide layer 16 tends to diffuse during these heat treatments. The barrier effect of the TEOS film 18 against fluorine is low, while metal or the silicon nitride film 22 has a high barrier effect to prevent the diffusion of fluorine. Therefore, when the above-described heat treatments are performed, F layers 24 having a high fluorine concentration are formed in the vicinities of the upper surface of the lower layer metal wiring 14, the bottom surface of the metal wiring 20, and the bottom surface of the silicon nitride film 22, as shown in FIG. 5. These F layers 24 may cause film blistering, film separation, or pattern separation to occur.
In devices of the quarter-micron generation, a metal wiring having a structure in which AlCu is sandwiched between Ti-based films are normally used. In such a metal wiring, when, for example, a Ti/TiN film is used, an F layer 24 is formed in the vicinity of Ti. In this case, Ti reacts with F, resulting in the condition to cause film separation more easily.
The above-described film blistering, film separation, or pattern separation causes metal wiring to be short-circuited. Therefore, the conventional structures of semiconductor devices, and the methods for producing such semiconductor devices have had problems of disadvantages to easily cause the lowering of product yield and the deterioration of reliability.
The present invention has been devised to solve the above-described problems, and a first object of the present invention is to provide a semiconductor device that realizes high reliability and high product yield while using a fluorine-containing silicon oxide film as the interlayer insulation film.
The above object of the present invention is achieved by a semiconductor device having an interlayer oxide film formed of a fluorine-containing silicon oxide film. The device includes a metal wiring formed in an upper layer of the fluorine-containing silicon oxide film. The device further includes an SiH4-based silicon oxide film existing only between the metal wiring and the fluorine-containing silicon oxide film.
The above object of the present invention is also achieved by a semiconductor device having an interlayer oxide film formed of a fluorine-containing silicon oxide film. The device includes a metal wiring formed in an upper layer of the fluorine-containing silicon oxide film. The device further includes a passivation film formed in the upper layer of the fluorine-containing silicon oxide film so as to cover the metal wiring. The passivation film comprises a low refraction factor silicon oxide film having a refraction factor lower than 1.48, and a silicon nitride film formed on the low refraction factor silicon oxide film.
The above object of the present invention is further achieved by a semiconductor device having an interlayer oxide film formed of a fluorine-containing silicon oxide film. The device includes a metal wiring formed in an upper layer of the fluorine-containing silicon oxide film. The metal wiring has a fluorination retardant metal layer that is difficult to react with fluorine at a bottom thereof.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.